A System-on-Chip (SoC) typically comprises tens of clocks derived from one or more main or reference clocks. Each of the derived clocks has to be verified to ensure it has the correct time period and duty cycle with respect to the main or reference clock.
Such clock verification is typically done using dynamic simulation based checkers/monitors. However, such a verification method takes several simulation cycles and test vectors to validate each reference clock-derived clock pair. Furthermore, building the checkers/monitors is a tedious process which takes significant time and is prone to human error.
Such a verification method is also not easily adaptable to last minute changes to the configuration of any of the derived clocks. In particular, while it may be easy to re-wire the clocks to meet new requirements, re-validating such a change requires re-testing the new design with a new set of test vectors and simulations which is not only practically difficult, but can cause a significant delay to the delivery of the final product and may reduce the quality of the verification.
The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known verification systems.